Mips processor architecture pdf

The early MIPS architectures were 32-bit, with 64-bit versions added later. V mips processor architecture pdf defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture. These uses were complemented by embedded applications at first, but during the 1990s, MIPS became a major presence in the embedded processor market, and by the 2000s, most MIPS processors were for these applications.

In the mid- to late-1990s, it was estimated that one in three RISC microprocessors produced was a MIPS processor. Both MIPS and the R2000 were introduced together in 1985. MIPS I has thirty-two 32-bit general-purpose registers. 0 is hardwired to zero and writes to it are discarded. 31 is the link register.

The program counter has 32 bits. The two low-order bits always contain zero since MIPS I instructions are 32 bits long and are aligned to their natural word boundaries. Instructions are divided into three types: R, I and J. Every instruction starts with a 6-bit opcode. J-type instructions follow the opcode with a 26-bit jump target. MIPS I has instructions that load and store 8-bit bytes, 16-bit halfwords, and 32-bit words. Since MIPS I is a 32-bit architecture, loading quantities fewer than 32 bits requires the datum to be either signed- or zero-extended to 32 bits.

All load and store instructions compute the memory address by summing the base with the sign-extended 16-bit immediate. MIPS I requires all memory accesses to be aligned to their natural word boundaries, otherwise an exception is signaled. The instruction in the load delay slot cannot use the data loaded by the load instruction. MIPS I has instructions to perform addition and subtraction.

The overflow check interprets the result as a 32-bit two’s complement integer. AND, OR, XOR, and NOR. These instructions source their operands from two GPRs and write the result to a third GPR. By default, the operands are interpreted as signed integers. The Load Immediate Upper instruction copies the 16-bit immediate into the high-order 16 bits of a GPR. It is used in conjunction with the Or Immediate instruction to load a 32-bit immediate into a register.

MIPS I has instructions to perform left and right logical shifts and right arithmetic shifts. MIPS I has instructions for signed and unsigned integer multiplication and division. For division, the quotient is written to LO and the remainder to HI. HI or LO to a GPR. These instructions are interlocked: reads of HI and LO do not proceed past an unfinished arithmetic instruction that will write to HI and LO. GPR to HI and LO.

These instructions are used to restore HI and LO to their original state after exception handling. Instructions that read HI or LO must be separated by two instructions that do not write to HI or LO. Unless the branch delay slot is filled by an instruction performing useful work, an nop is substituted. Jumps have two versions: absolute and register-indirect. 26-bit instr_index left by two bits and concatenating the 30-bit result with the two high-order bits of instruction in the branch delay slot address’s. The address sourced from the GPR must be word-aligned, else an exception is signaled after the instruction in the branch delay slot is executed. The “Jump and Link Register” instruction permits the return address to be saved to any writable GPR.

MIPS I has two instructions for software to signal an exception: System Call and Breakpoint. Breakpoint is used to transfer control to a debugger via the kernel’s exception handler. Both instructions have a 20-bit Code field that can contain operating environment-specific information for the exception handler. MIPS has 32 floating-point registers. Two registers are paired for double precision numbers. Loads the 4 byte word stored from: MEM into a Coprocessor data register. Stores the 4 byte word held by a Coprocessor data register into: MEM.

A set of Trap-on-Condition instructions were added. These instructions caused an exception if the evaluated condition is true. These instructions improve performance in certain cases by allowing useful instructions to fill the branch delay slot. Consistent with other memory access instructions, these loads and stores required the doubleword to be naturally aligned. The instruction set for the floating point coprocessor also had several instructions added to it. An IEEE 754-compliant floating-point square root instruction was added. It supported both single- and double-precision operands.

A set of instructions that converted single- and double-precision floating-point numbers to 32-bit words were added. These complemented the existing conversion instructions by allowing the IEEE rounding mode to be specified by the instruction instead of the Floating Point Control and Status Register. MIPS II implementations because the introduction of the 64-bit MIPS III architecture in 1991 left MIPS II as the newest 32-bit MIPS architecture until MIPS32 was introduced in 1999. LO registers, and program counter to 64 bits to support it. Existing instructions originally defined to operate on 32-bit words were redefined, where necessary, to sign-extend the 32-bit results to permit words and doublewords to be treated identically by most instructions. In MIPS III it sign-extends words to 64 bits.

MIPS III to provide three 64-bit versions of each MIPS I shift instruction. 64 bits can be specified. The third version obtains the shift distance from the six low-order bits of a GPR. The remaining coprocessors gained instructions to move doublewords between coprocessor registers and the GPRs. 64 bits and the requirement for instructions to use even-numbered register only was removed. MIPS I- and II-compatible mode. The floating-point control registers were not extended for compatibility.

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